This invention relates to a semiconductor device, specifically to a semiconductor device preventing a weak inversion leakage current while minimizing a die size.
FIG. 3 and FIG. 4 are a cross-sectional view and a top view illustrating a prior art device.
A gate electrode 55 is disposed on a first gate insulation film 53 and a second gate insulation film 54, which is thicker than the first gate insulation film 53, formed in areas other than areas of a device isolation film 52 on a semiconductor substrate 51 of a first conductivity e.g. P-type, as shown in the figures.
Low impurity concentration N-type source and drain regions (Nxe2x88x92 layers, drift layers) 56 and 57 are disposed adjacent to the gate electrode 55 through the second gate insulation film 54.
High impurity concentration N-type source and drain regions (N+ layers) 58 and 59 are disposed between the second gate insulation film 54 and the device isolation film 52.
Together with a channel region 60, which is a surface region of the semiconductor substrate 51 between the source and drain regions 56 and 57 under the first gate insulation film 53, the structure described above makes a so-called LOCOS offset-type semiconductor device.
A conventional transistor is basically shaped like a rectangle. It requires convex regions (shaded regions in FIG. 4) protruding from the N-layers 56 and 57 as shown in FIG. 4, in order to suppress a weak inversion leakage current.
A width S2 of a minimum transistor of the prior art is increased by a width of the convex regions required to suppress the weak inversion leakage current.
Thus, the size of a transistor in a high voltage logic circuitry becomes larger than that required for a driving capacity, resulting in an increased die size.
A semiconductor device of this invention is directed to solve the problem addressed above. A gate electrode formed on a substrate of a first conductivity through a gate insulation film and source and drain regions of an opposite conductivity formed adjacent to the gate electrode are polygonal in shape.
The gate electrode and the source and drain regions can also be octagonal in shape.